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US Patent Alert: USPTO Implements New Expedited Examination: Semiconductor Technology Pilot Program

Updated: Jan 12

The US Patent and Trademark Office now offers a Semiconductor Technology Pilot Program. The Program is intended to expedite examination of patent applications for innovations that "increase semiconductor device production, reduce semiconductor manufacturing costs, and strengthen the semiconductor supply chain." (See Semiconductor Technology Pilot Program | USPTO).

Qualifying applications directed to processes or apparatus for manufacturing semiconductor devices will be advanced out of turn for examination until a first Office Action is issued. Petitions to make special under this program will be accepted until December 2, 2024, or until 1,000 applications have been granted special status under this program, whichever occurs earlier.

Timing: A qualifying applicant must file a petition to make special under this program within 30 days of the U.S. filing date.

Fees: USPTO government fees are waived. No petition fee is required.

Eligibility: Only 1) "non-continuing" original utility nonprovisional patent applications and 2) original utility nonprovisional patent applications that claim the benefit of a filing date under 35 U.S.C. 120, 121, 365(c), or 386(c) of only one prior application that is either a nonprovisional application or an international application designating the US.

Technology Requirement: Only patent applications having a claim that covers a process or an apparatus for manufacturing a semiconductor device and that corresponds to one or more of the technical concepts within H10 (semiconductor Devices; Electric Solid-State Devices Not Otherwise Provided For) or H01L (Semiconductor Devices Not Covered By Class 10) in the Cooperative Patent Classification Sytem.

Our team is experienced in protecting inventions for clients in the semiconductor industry. Contact us if you have questions about protecting your semiconductor innovations, using the Semiconductor Technology Pilot Program, or accelerating US patent examination by other means. (See ADJUSTING SPEED OF U.S. PATENT EXAMINATION (

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